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dc.contributor Matthews, Thomas W. en
dc.contributor.advisor Heedley, Perry L. en
dc.contributor.author Grandhi, Sri Harsha en
dc.date.accessioned 2017-05-16T14:51:18Z en
dc.date.available 2017-05-16T14:51:18Z en
dc.date.issued 2017-05-16 en
dc.date.submitted 2017-04-28 en
dc.identifier.uri http://hdl.handle.net/10211.3/191241 en
dc.description Project (M.S., Electrical and Electronic Engineering)--California State University, Sacramento, 2017. en
dc.description.abstract A phase-locked loop (PLL) is widely used on many integrated circuits to provide an accurate and stable clock. A PLL uses negative feedback around an on-chip oscillator that the feedback loop constantly adjusts to match the phase and frequency of an input reference clock. This project focused on the design of a crystal oscillator in 0.18 um CMOS, which is used to provide an accurate reference clock for an all digital phase-locked loop. This design makes use of an on-chip oscillator which utilizes an external off-chip crystal to provide a highly accurate frequency. The crystal oscillator circuit was designed using Cadence Virtuoso computer-aided design (CAD) software, and verified using the Spectre circuit simulator across different process, supply voltage, and temperature (PVT) variations. en
dc.description.sponsorship Electrical and Electronic Engineering en
dc.language.iso en_US en
dc.subject Crystal oscillator en
dc.subject Common source amplifier en
dc.subject Phase locked loop en
dc.title Design of a crystal oscillator for an all-digital phase-locked loop in 0.18um CMOS en
dc.type Project en

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